Principal FPGA Design Engineer - Oxfordshire
CV-LibraryOxford, OxfordshirepermanentPosted: 25 September 2026
Apply NowRole: Principal FPGA Design Engineer
Location: Oxfordshire
Package: £80k - £120k + Bonus + Generous Benefits
About the Business:
We are partnering with a pioneering UK technology innovator developing next-generation medical device technologies. Operating globally, they combine hardware, custom silicon, and complex data processing to transform global healthcare and scientific research.
Role Overview:
A hands-on technical leadership and mentorship position, owning the architecture and delivery of high-throughput FPGA subsystems. You will drive designs across the full lifecycle-from initial requirements through RTL implementation, custom-ASIC bring-up, lab validation, and product release.
Key Responsibilities:
System Architecture: Lead FPGA subsystem architecture for complex data platforms.
RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains.
Optimization: Maximize throughput, power efficiency, resource usage, and timing closure.
Integration: Collaborate with ASIC, FW, and SW teams to support board bring-up.
Leadership: Champion CI/CD automation and mentor mid/senior hardware engineers.What We Need:
Proven full-lifecycle FPGA design experience (architecture to hardware bring-up).
Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa).
Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging tools.
Scripting for workflow automation (Python, Tcl, Make).
Degree in Electronic Engineering or equivalent industry background.Apply:
Interested in leading core architecture on high-impact technology? Apply with your CV today for a confidential discussion
Location: Oxfordshire
Package: £80k - £120k + Bonus + Generous Benefits
About the Business:
We are partnering with a pioneering UK technology innovator developing next-generation medical device technologies. Operating globally, they combine hardware, custom silicon, and complex data processing to transform global healthcare and scientific research.
Role Overview:
A hands-on technical leadership and mentorship position, owning the architecture and delivery of high-throughput FPGA subsystems. You will drive designs across the full lifecycle-from initial requirements through RTL implementation, custom-ASIC bring-up, lab validation, and product release.
Key Responsibilities:
System Architecture: Lead FPGA subsystem architecture for complex data platforms.
RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains.
Optimization: Maximize throughput, power efficiency, resource usage, and timing closure.
Integration: Collaborate with ASIC, FW, and SW teams to support board bring-up.
Leadership: Champion CI/CD automation and mentor mid/senior hardware engineers.What We Need:
Proven full-lifecycle FPGA design experience (architecture to hardware bring-up).
Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa).
Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging tools.
Scripting for workflow automation (Python, Tcl, Make).
Degree in Electronic Engineering or equivalent industry background.Apply:
Interested in leading core architecture on high-impact technology? Apply with your CV today for a confidential discussion